Quantum Transport in Ultrasmall Devices

Quantum Transport in Ultrasmall Devices

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The operation of semiconductor devices depends upon the use of electrical potential barriers (such as gate depletion) in controlling the carrier densities (electrons and holes) and their transport. Although a successful device design is quite complicated and involves many aspects, the device engineering is mostly to devise a qbestq device design by defIning optimal device structures and manipulating impurity profIles to obtain optimal control of the carrier flow through the device. This becomes increasingly diffIcult as the device scale becomes smaller and smaller. Since the introduction of integrated circuits, the number of individual transistors on a single chip has doubled approximately every three years. As the number of devices has grown, the critical dimension of the smallest feature, such as a gate length (which is related to the transport length defIning the channel), has consequently declined. The reduction of this design rule proceeds approximately by a factor of 1. 4 each generation, which means we will be using 0. 1-0. 15 ). lm rules for the 4 Gb chips a decade from now. If we continue this extrapolation, current technology will require 30 nm design rules, and a cell 3 2 sizeProceedings of a NATO Advanced Study Institute on Quantum Transport in Ultrasmall Devices, held July 17a€“30, 1994, in II Ciocco, Italy David ... of the structures, the decomposition gives evidence, that the simple assignment indicated in the experimental data is not justified. ... are spacially separated from the scatterers (Fig. 10). This effect can be increased by introducing a spacer and has led to record 94.


Title:Quantum Transport in Ultrasmall Devices
Author: David Ferry, Harold L. Grubin, Carlo Jacoboni, A.-P. Jauho
Publisher:Springer Science & Business Media - 2012-12-06
ISBN-13:

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